IEEE S.F. Bay Area Council e-GRID's
BayAreaTech

TUESDAY September 28, 2010
SCV Solid State Circuits, with Electron Devices and Computer Chapters
Speakers: David C. Brock, Senior Research Fellow, Center for Contemporary History and Policy, Chemical Heritage Foundation; Christophe Lecuyer, Principal Economic Analyst, Office of the President, University of California
Time: Presentations at 6:00 PM
Cost: none
Place: National Semiconductor Building E Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: EventBrite, from website
Web: ewh.ieee.org/mu/scv-sscs
In the first three and a half years of its existence, Fairchild Semiconductor developed, produced, and marketed the device that would become the fundamental building block of the digital world: the microchip.  Founded in 1957 by (more…)

FRIDAY September 17, 2010
SCV Consultants’ Network of Silicon Valley
Speaker: Peter Salmon, individual inventor
Time: 9:00 AM - 12:30 PM
Cost: IEEE members $35; non-members $45; also available as a webcast
Place: Cogswell Polytechnical College, Board Room, 1175 Bordeaux Drive, Sunnyvale
RSVP: through website
Web: www.eventbee.com/view/ieeecnsv091710/track/sfbac1b

This seminar, our second in the “Patents” series, will address inventing and patenting from the perspective of an individual inventor, Peter Salmon.  If you have invented a completely new product or, something that just (more…)

TUESDAY November 16, 2010
SCV Consultants’ Network of Silicon Valley
Speaker: Dr. Kendall Waters, IP and Technology Development, Silicon Valley Medical Instruments, Inc.
Time: Presentation at 7:00 PM
Cost: none
Place: KeyPoint Credit Union, 2805 Bowers Ave., Santa Clara
RSVP: not required
Web: www.CaliforniaConsultants.org

Successfully taking a medical device product from concept to regulatory approval requires a broad range of expertise. Effective strategy execution requires having the right talents available at (more…)

WEDNESDAY September 1, 2010
SCV Circuits and Systems Chapter
Speaker: Massimo Alioto, Ph.D, Visiting Professor at BWRC — UC-Berkeley
Time: Networking/light dinner at 6:30 PM; Presentation at 7:00 PM
Cost: $2 donation accepted for food
Place: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/cas

In the last years, subthreshold CMOS logic circuits have become very popular in ultra low power applications, which typically constrain the power budget to a few tens of uWs and the supply voltage to (more…)

WEDNESDAY September 15, 2010
SCV Education Chapter
Speaker: Dr. Steven R. Hetzler, IBM Fellow, Manager Storage Architecture Research
Time: Networking & food at 6:30 PM; Presentation at 7:00 PM
Cost: $2 donation for food
Place: Biltmore Hotel, 2151 Laurelwood Road, Santa Clara
RSVP: see website
Web: essv915.eventbrite.com

The pace of technology advancement in recent years is a wonder to behold. Examples abound in wireless communications, computing, biotech and data storage. It wasn’t that long ago that a GB was a massive amount of data storage. As astounding as these changes have been, we have come to expect faster gains in the future. Continuing self-education will likely be required for engineers and business leaders to remain competitive. This will make teaching students how to learn of the most valuable products of the education system. Even non science graduates will need to know how to identify problems, and separate facts from the assumptions.
Examples from my career will be used to examine this hypothesis. A particularly poignant example arises from my recent work on Chasm Analysis, which I created as a method for identifying the market potential for storage technologies, by examining the foundations from an economic perspective. The key insight comes from identifying an incorrect assumption made by technologists since the 1960s. It has proven quite useful in forecasting the future of solid state storage in the Information Technology (IT) space.  It also provides support for the need to employ the scientific method to the business of technology, and the need to continually reeducate one’s self.

THURSDAY September 16, 2010
SCV Control Systems Chapter
Speaker: Dave Stevens, Stevens Law Group, P.C.
Time: Networking and refreshments at 6:30 PM; Presentation at 7:00 PM
Cost: none
Place: Cogswell Polytechnical College, Board Room, 1175 Bordeaux Drive, Sunnyvale
RSVP: not required
Web: ewh.ieee.org/r6/scv/css

This presentation from a legal expert outlines general principles of intellectual property (IP) protection for various technologies, and will provide practical strategic planning tools and roadmaps for (more…)

TUESDAY September 21, 2010
SCV Magnetics Chapter
Speaker: Barry Stipe, Hitachi Global Storage Technologies
Time: Networking and pizza at 7:00 PM; Presentation at 7:30 PM
Cost: none
Place: Western Digital, 1710 Automation Parkway, San Jose
RSVP: not required
Web: ewh.ieee.org/r6/scv/mag

Thermally-Assisted Magnetic Recording (TAR) and Bit Patterned Recording (BPR) are two of the most promising technologies for surpassing the fundamental limitations of conventional magnetic (more…)

TUESDAY September 21, 2010
SCV Nanotechnology Chapter
Speaker: Dr. Phil Metz, Director of Business Development, SolFocus
Time: Registration & light lunch 11:30 AM; Presentation at 12:00 Noon
Cost: IEEE Members and Students $5; Non-Members $10
Place: National Semiconductor Bldg E-1 CMA Room. 2900 Semiconductor Drive, Santa Clara
RSVP: from the website
Web: www.ieee.org/nano

This presentation introduces the SolFocus Concentrator Photovoltaic (CPV) product – what it is and how it works.  It presents the value proposition for SolFocus CPV and the design and manufacturing advantages of this product vs. other (more…)

TUESDAY October 12, 2010
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Prof. Rao Tummala, Founding Director, NSF Packaging Research Center, Georgia Tech
Time: Optional dinner at 6:00 PM; Presentation at 6:45 PM
Cost: $20 for dinner; Students & unemployed members $10 (no cost for presentation-only)
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: From the website
Web: www.cpmt.org/scv

Nanopackaging has been defined as the process of interconnecting, powering, cooling, and protecting the nanocomponents made of nanomaterials to form electronic and bioelectronic systems for greatly improved (more…)

TUESDAY August 17, 2010
SCV Nanotechnology Chapter
Speaker: Jingjing Li, Information and Quantum Systems Lab, Hewlett-Packard Laboratories
Time: Registration & light lunch 11:30 AM; Presentation at 12:00 Noon
Cost: IEEE Members and Students $5; Non-Members $10
Place: National Semiconductor Bldg E-1 CMA Room. 2900 Semiconductor Drive, Santa Clara
RSVP: from the website
Web: www.ieee.org/nano

Controlling the propagation and localization of light at the sub-wavelength dimension is the basis of the design of many optical devices widely used in engineering and fundamental science (more…)