IEEE S.F. Bay Area Council e-GRID's
BayAreaTech

SATURDAY February 7, 2009
SCV Signal Processing Chapter
Speakers: Dr. Xiaoshu Qian, Intel; Prof. Tokunbo Ogunfunmi, Santa Clara U; Dr. Chris Dick, Xilinx; Prof. Chang Choo, SJSU; Dr. Jim Hwang, Xilinx
Time: 8:00 AM - 5:00 PM
Cost: $70 for IEEE members, $80 for non-members, $30 for students (includes workshop proceedings, light breakfast, and lunch)
Place: Bannan Engineering Laboratories, Santa Clara University
RSVP: on the website
Web: ewh.ieee.org/r6/scv/sps/fpgaSPS

Topics at a glance

(1) Why and when to use DSPs, FPGAs and ASICs
Speaker: Dr. Xiaoshu Qian, Intel Corporation
(2) FPGA Architectures for H.264 Video Processing
Speaker: Prof. Tokunbo Ogunfunmi, Santa Clara University
(3) FPGAs: Re-inventing the Signal Processor and MIMO-OFDM Applications
Speaker: Dr. Chris Dick, Xilinx Corporation
(4) FPGA-Based Embedded Wideband Audio Codec System
Speaker: Prof. Chang Choo, San Jose State University
(5) A Platform-Based Approach to Realizing High-Performance DSP Subsystems in FPGAs
Speaker: Dr. Jim Hwang, Xilinx Corporation

THURSDAY February 5, 2009
SF GOLD (Grads of the Last Decade) Chapter
Event: an opportunity to network with fellow IEEE members and engineers, grab a bite and drink, and meet the officers
Time: 6:15 PM
Cost: none (except for your food/drink)
Place: “The Holding Company” 2 Embarcadero Center Promenade Level, San Francisco
RSVP: by email to Frank Oppong, sfgold.r6@gmail.com
Web: www.ewh.ieee.org/r6/san_francisco/gold

Happy new year!  Please join IEEE SF GOLD (Graduates of the Last Decade) for our first meeting of the year.  It will be an opportunity to network with fellow IEEE members, engineers and local (more…)

THURSDAY February 5, 2009
SCV Technology Management Chapter
Speaker: ArLyne Diamond, Ph.D., Professional and Organizational Development
Time: Guided Networking at 6:30 PM; Dinner at 7:15 PM; Presentation at 7:45 PM
Cost: Cost: $25 (IEEE member), $30 (non member); Cash or check at the door; +$5 without reservation
Place: Ramada Inn, 1217 Wildwood Ave, Sunnyvale
RSVP: through Website
Web: www.ieee-scv-ems.org

Decisions and demands come from above, and the manager is the one responsible for seeing to it that staff deliver the products in a quality and timely manner.  On the other hand, we are living in an age (more…)

TUESDAY February 3, 2009
SCV Lasers and Electro Optics Chapter, with Product Safety Engineering Chapter
Subject: Breakdown Spectroscopy (LIBS)
Speaker: Dr. Rick Russo, Applied Spectra, Inc.
Time: Networking/Pizza Social 6:00 PM, Presentation at 7:00 PM
Cost: none
Place: National Semiconductor Building E Auditorium, 2900 Semiconductor Drive, Santa Clara
RSVP: see web link for EventBrite
Web: www.ewh.ieee.org/r6/scv/leos

With recent adoption of RoHS (Restriction on Hazardous Substances) initiative by many Asian and European countries, electronic product manufacturers and their component suppliers are banned from using (more…)

WEDNESDAY February 25, 2009
SCV Reliability Chapter
Speakers: Chapter members who attended
Time: Refreshments at 6:30 PM; Presentations at 7:00 PM
Cost: none
Place: HP Oak Room, 19447 Pruneridge Avenue (Building 48), Cupertino
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/rl

The 55th Annual Reliability and Maintainability Symposium (RAMS) was held in Fort Worth on January 26-29, 2009. For those of you that couldn’t attend, we will bring the symposium to you (except for the Texas accents). This evening (more…)

WEDNESDAY March 11, 2009
SCV Components, Packaging & Manufacturing Technology Chapter
Speaker: Dr. Christopher Sellathamby, Vice President, Scanimetrics
Time: Optional dinner at 6:30 PM; Presentation at 7:30 PM
Cost: $25 if reserved by March 9; $30 at door (no cost for presentation)
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: via the DoubleKnot registration page, from website
Web: www.cpmt.org/scv

The continued demand for smaller microchips and better performance has created a crisis in interconnectivity between chips – input/output (I/O) data throughput is a bottleneck in high-speed chip-to-chip (more…)

TUESDAY February 10, 2009
SCV Electron Devices Chapter
Speaker: Alan K. Allen, Intel Corp./SEMATECH
Time: Social/food at 6:00 PM, Presentatoin at 6:15 PM
Cost: none
Place: National Semiconductor Corp. Building E-1 - Auditorium CMA, 2900 Semiconductor Drive, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/eds

A review will be presented of the 2008 International Technology Roadmap for Semiconductors (ITRS) Update which was completed in December, 2008.  In particular, the messages presented (more…)

TUESDAY April 7, 2009
SCV Lasers and Electro Optics Chapter
Speaker: Dr. Dieter Jundt, Crystal Technology, Inc.
Time: Networking/Pizza Social 6:00 PM, Presentation at 7:00 PM
Cost: none
Place: National Semiconductor Building E Auditorium, 2900 Semiconductor Drive, Santa Clara
RSVP: use web link for EventBrite
Web: www.ewh.ieee.org/r6/scv/leos

RGB laser displays offer several advantages over currently available display types.  The color gamut is larger than in CRT, LED or Plasma systems, offering more vibrant colors.  (more…)

TUESDAY March 24, 2009
SF Industry Applications Chapter
Speaker: Armen Kludjian, Peterson Power Systems
Time: Social at 5:30 PM, Presentation at 6:00 PM, Dinner at 7:00 PM
Cost: $25 (At the door); $10 for student members
Place: Sinbad’s Restaurant, Pier 2 The Embarcadero, San Francisco
RSVP: by email to Frank Sylvester, frank.sylvester@sfdpw.org, 415.558.4591
Web: www.e-grid.net/docs/0903-sf-ias.pdf

Our March speaker will discuss the following topics:
1)    EPA/CARB Certification, required by BAAQMD, ATCM, BACT, Tier 2-3-4, SCR Systems (more…)

International Symposium on Quality Electronic Design
– March 16-18, 2009     — DoubleTree Hotel, San Jose
– 6 Tutorials   — Sessions (140 papers)   — Keynotes   — Exhibits
– Leading Design for Quality and Manufacturability
Technical Sessions:   - Aging-Aware Design   - Robust Circuits, Library & Modeling   - Emerging Technologies   - Noise and Variation Tolerance   - PProcess Variation   - System and Interface Validation   - Co-design Applications for IC Packaging   - Memory Design Solutions   - Clock and Noise   - Low-Voltage Design   - Timing Analysis and Floor Planning   - Variation-Tolerant Design   - System Power and Reliability … and more
Full-day Tutorials:   — Low-Power Variation-Tolerant Logic Circuits   — Low power SRAM and FinFet Design for Nano-Scale Era   — The Promise of Phase-Change Memory   — Statistical Techniques for Analog Circuits   — 3-D CAD Design/Technology   — Multi-coring: Pros and cons
Full information and registration: www.isqed.org