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February 21, 2012

Mtg: Outlook and Challenges in Electrostatic Discharge (ESD) Protection of Modern and Future Integrated Circuits

by @ 11:08 am. Filed under ALL, Electronics Design, Semiconductors
 

FRIDAY February 24, 2012
Stanford Electron Devices Student Chapter
Speaker: Dr. Juin J. Liou, Distinguished Professor, University of Central Florida
Time: Presentation at 3:30PM, Pizza to follow
Cost: none
Place: Packard 101, Stanford University, Stanford
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/mag

Electrostatic discharge (ESD) is one of the most prevalent threats to electronic components. It is an event in which a finite amount of charge is transferred from one object (i.e., human body) to the other (i.e., microchip). This process can result in a very high current passing through the microchip within a very short period of time, and more than 35% of chip damages can be attributed to such an event.  As such, designing on-chip ESD structures to protect microchips against the ESD stress is a high priority in the semiconductor industry. The continuing scaling of CMOS technology makes the ESD-induced failures even more prominent, and one can predict with certainty that the availability of effective and robust ESD protection solutions will become a critical and essential component to the successful advancement and commercialization of the next-generation CMOS technology.
An overview on the ESD sources, models, protection schemes, and testing will first be given in this talk. This is followed by the discussions of the challenges for designing and realizing ESD protection solutions in modern and next-generation integrated circuits.

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