IEEE S.F. Bay Area Council e-GRID's
BayAreaTech

THURSDAY July 19, 2012
SCV Solid State Circuits Chapter
Speaker: Jafar Savoj, Xilinx, Inc.
Time: Refreshments at 6:00 PM; Presentation at 6:30 PM
Cost: none
Place: Texas Instruments Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: not required
Web: sites.ieee.org/scv-sscs

This talk describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA.? The wide common mode receive AFE utilizes a three-stage CTLE to provide selective frequency boost for long-tail ISI cancellation.? A 5-tap speculative DFE removes the immediate post-cursor ISI.? Both CTLE and DFE are fully adaptive using sign-sign LMS algorithm.? A novel clocking technique uses wideband LC and ring oscillators for reliable clocking from 0.6-12.5Gb/s operation.? The transmitter utilizes a 3-tap FIR and provides flexibility for supply and ground referenced operation.? The transceiver achieves BER < 10-15 over a 33dB-loss backplane at 12.5Gb/s and over multiple channels with 10G-KR characteristics at 10.3125Gb/s.