IEEE S.F. Bay Area Council e-GRID's
BayAreaTech

TUESDAY September 18, 2012
SCV Consultants’ Network of Silicon Valley
Speaker: Jim Ready, Cadence Design Systems
Time: Presentation at 7:00 PM
Cost: none
Place: KeyPoint Credit Union, 2805 Bowers Ave., Santa Clara
RSVP: not required
Web: www.CaliforniaConsultants.org

Moore’s law continues to drive the development of increasingly complex semiconductor devices, most notably the SoC (System on a Chip). However, silicon designers have now hit a significant constraint in utilizing the seemingly infinite number of transistors available to them when trying to increase processor performance: they have reached a point where they are limited by the power consumption (and heat) generated by simply increasing clock speed to gain performance.
In response, the industry has embarked upon a disruptive change by increasing performance through processors composed of multiple computing cores, essentially turning to parallel computing as the new performance driver. In addition, certain computing environments use an additional “trick” to increase system performance by adding application-specific hardware offload engines along with multiple computing cores to accelerate overall SoC performance.
Both of these approaches have significant implications for both the operating system and the applications running on an SoC. While the simple answer has always been to invoke the “magic” of virtualization to provide a flexible software framework for these advanced SoCs, reality says otherwise. This talk will illustrate the limits of virtualization (at least as currently available) and describe some new operating system approaches that look to provide a better fit between the advanced SoC hardware and the application software.