Technology & Networking in Silicon Valley & the SF Bay Area: Upcoming Meetings, Courses and Conferences
WEDNESDAY September 8, 2010
SCV Communications Chapter
Speakers: Sanjay Kasturia and Jose Tellado, Teranetics; George Ginis, ASSIA, Inc
Time: Networking with refreshments at 6:00 PM; Presentations at 6:30 PM, followed by panel
Cost: none
Place: National Semiconductor, Building E, Conference Room, 2900 Semiconductor Dr, Santa Clara
RSVP: From the website
Web: www.ewh.ieee.org/r6/scv/comsoc
This session will address the challenges of high speed twisted pair-based communications in data centers/enterprises (LAN) and wireline access (DSL). There will be two talks followed by (more…)
TUESDAY September 28, 2010
SCV Solid State Circuits, with Electron Devices and Computer Chapters
Speakers: David C. Brock, Senior Research Fellow, Center for Contemporary History and Policy, Chemical Heritage Foundation; Christophe Lecuyer, Principal Economic Analyst, Office of the President, University of California
Time: Presentations at 6:00 PM
Cost: none
Place: National Semiconductor Building E Auditorium, 2900 Semiconductor Dr., Santa Clara
RSVP: EventBrite, from website
Web: ewh.ieee.org/mu/scv-sscs
In the first three and a half years of its existence, Fairchild Semiconductor developed, produced, and marketed the device that would become the fundamental building block of the digital world: the microchip. Founded in 1957 by (more…)
WEDNESDAY September 1, 2010
SCV Circuits and Systems Chapter
Speaker: Massimo Alioto, Ph.D, Visiting Professor at BWRC — UC-Berkeley
Time: Networking/light dinner at 6:30 PM; Presentation at 7:00 PM
Cost: $2 donation accepted for food
Place: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/cas
In the last years, subthreshold CMOS logic circuits have become very popular in ultra low power applications, which typically constrain the power budget to a few tens of uWs and the supply voltage to (more…)
TUESDAY August 31, 2010
SCV Consumer Electronics
Subject:
Speaker: Chandlee Harrell, Silicon Image
Time: Networking/refreshments at 6:30 PM; Presentation at 7:00 PM
Cost: $10 for non-members, $5 foe IEEE members, free for IEEE CES members & Student IEEE members
Place: Hewlett Packard, Building 20, 3000 Hanover St., Palo Alto
RSVP: from the website
Web: ewh.ieee.org/r6/scv/ce
HDMI (High-Definition Multimedia Interface) is that now-familiar interface that you use to connect video and audio to your HDTV set. It has gone through a number of improvements since it first (more…)
WEDNESDAY September 15, 2010
SCV Education Chapter
Speaker: Dr. Steven R. Hetzler, IBM Fellow, Manager Storage Architecture Research
Time: Networking & food at 6:30 PM; Presentation at 7:00 PM
Cost: $2 donation for food
Place: Biltmore Hotel, 2151 Laurelwood Road, Santa Clara
RSVP: see website
Web: essv915.eventbrite.com
The pace of technology advancement in recent years is a wonder to behold. Examples abound in wireless communications, computing, biotech and data storage. It wasn’t that long ago that a GB was a massive amount of data storage. As astounding as these changes have been, we have come to expect faster gains in the future. Continuing self-education will likely be required for engineers and business leaders to remain competitive. This will make teaching students how to learn of the most valuable products of the education system. Even non science graduates will need to know how to identify problems, and separate facts from the assumptions.
Examples from my career will be used to examine this hypothesis. A particularly poignant example arises from my recent work on Chasm Analysis, which I created as a method for identifying the market potential for storage technologies, by examining the foundations from an economic perspective. The key insight comes from identifying an incorrect assumption made by technologists since the 1960s. It has proven quite useful in forecasting the future of solid state storage in the Information Technology (IT) space. It also provides support for the need to employ the scientific method to the business of technology, and the need to continually reeducate one’s self.
MONDAY October 18, 2010
SCV Circuits and Systems Chapter
Speaker: Prof. Richard Shi, University of Washington
Time: Networking/light dinner at 6:30 PM; Presentation at 7:00 PM
Cost: $2 donation accepted for food
Place: QualComm Santa Clara, Building B, 3165 Kifer Road, Santa Clara
RSVP: not required
Web: www.ewh.ieee.org/r6/scv/cas
Verification is becoming the number-one bottleneck in mixed-signal systems-on-chip (SoC) design. This talk introduces a new design and verification methodology based on the automated generation of (more…)
TUESDAY October 5, 2010
OEB Life Members Group
Speaker/organizer: Charles Herget, Lawrence Livermore National Laboratory (retired)
Time: Networking, buffet dinner, discussion from 6:00 PM - 8:00 PM
Cost: $10 for buffet dinner
Place: Willow Tree Restaurant, 6513 Regional St, Dublin
RSVP: by email by October 1, to rsvp@ieee4life.org
Web: www.ieee4life.org
The first meeting of the Oakland/East Bay Life Member’s Affinity Group will be held on Tuesday, October 5, 2010, at the Willow Tree Restaurant in Dublin. This meeting will be an informal gathering to (more…)
TUESDAY September 28, 2010
SCV Product Safety Engineering Chapter
Speaker: Rick Row, Consultant
Time: Optional dinner at 5:30 PM; Presentation at 7:00 PM
Cost: no-host dinner at El Torito Mexican Restaurant; no cost for presentation
Place: Dinner at El Torito Mexican Restaurant, 2950 Lakeside Drive, Santa Clara; Meeting at Applied Materials, Bowers Café, 3090 Bowers Ave, Santa Clara
RSVP: not required
Web: ewh.ieee.org/r6/scv/pses
Three trends make mineral sourcing an issue of potentially compelling interest to product safety engineers. First, many more minerals are used today in manufacturing electronics than just a couple of (more…)
TUESDAY September 21, 2010
SCV Magnetics Chapter
Speaker: Barry Stipe, Hitachi Global Storage Technologies
Time: Networking and pizza at 7:00 PM; Presentation at 7:30 PM
Cost: none
Place: Western Digital, 1710 Automation Parkway, San Jose
RSVP: not required
Web: ewh.ieee.org/r6/scv/mag
Thermally-Assisted Magnetic Recording (TAR) and Bit Patterned Recording (BPR) are two of the most promising technologies for surpassing the fundamental limitations of conventional magnetic (more…)
TUESDAY October 12, 2010
SCV Components, Packaging and Manufacturing Technology Chapter
Speaker: Prof. Rao Tummala, Founding Director, NSF Packaging Research Center, Georgia Tech
Time: Optional dinner at 6:00 PM; Presentation at 6:45 PM
Cost: $20 for dinner; Students & unemployed members $10 (no cost for presentation-only)
Place: Biltmore Hotel, 2151 Laurelwood Rd (Fwy 101 at Montague Expressway), Santa Clara
RSVP: From the website
Web: www.cpmt.org/scv
Nanopackaging has been defined as the process of interconnecting, powering, cooling, and protecting the nanocomponents made of nanomaterials to form electronic and bioelectronic systems for greatly improved (more…)
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